1/9 axelite confidential materials, do not copy or distribute without written consent. rev.1.5 aug.24, 2011 a x1250s 1.5a sink/source bus termination regulator ? general description AX1250S is a linear regulator desig ned as a cost-effective solution for active termination of ddr sdram. the converting vo ltage range is from 1.3v to 5.5v into a desired output voltage, which is adjusted by two external resistors. the current sourcing and sinking capability of the r egulator is up to 1.5a while the output voltage within 2%. this device provides on-chip thermal shutdown and current limit functions for circuit tolerance of the output fault conditions. so p-8l package is availa ble for all commercial and industrial surface mount applications. ? features - ideal for ddr-i, ddr-ii an d ddr-iii applications - capable of sourcing and sinking current 1.5a - integrated power mosfets - current limiting protection - thermal shutdown protection - high accuracy output vo ltage at full load - output voltage traces refen pin voltage - low external component count - shutdown for standby or suspend mode operation with high-impedance output - sop-8l pb-free package.
2/9 axelite confidential materials, do not copy or distribute without written consent. rev.1.5 aug.24, 2011 a x1250s ? block diagram enable thermal shutdown current- limit error amplifier and soft-start power-on- reset vcntl vin vout gnd vref en v ref thsd por ? pin assignment the package of AX1250S is sop-8l; the pin assignment is given by: ( top view ) 1 2 3 4 8 7 6 5 vout gnd refen vin vcntl vcntl vcntl vcntl sop-8l name description vin input voltage pin gnd ground pin refen reference voltage input and chip enable pin vout output voltage pin vcntl supply input and gate drive voltage pin ? order/marking information order information top marking
3/9 axelite confidential materials, do not copy or distribute without written consent. rev.1.5 aug.24, 2011 a x1250s ? absolute maximum ratings (t a =25c) characteristics symbol rating unit v in supply voltage v in 6 v control voltage v cntl 6 v power dissipation pd internally limited w storage temperature range t st -65 to +150 c thermal resistance from junction to case jc 20 c/w thermal resistance from junction to ambient ja 60 c/w note: ja is measured with the pcb copper area (need connect to all v cntl pins) of approximately 1.5 in 2 (multi-layer). ? operating ratting parameter symbol value unit input voltage v in 1.3 to v cntl v control voltage v cntl 5 or 3.3 v ambient temperature t a -40 to +85 c junction temperature t j -40 to +125 c note: v os offset is the voltage measurement defined as v out subtracted from v refen . ? electrical characteristics v in =2.5v, v cntl =3.3v, v refen =1.25v, c out =10f (ceramic), t a =25c, unless otherwise specified characteristics symbol conditions min typ max units gate drive voltage range v cntl - 3.3 5.5 v por threshold v cntlrth - 2.5 - v por hysteresis v cntl - 0.1 - v input voltage v in 1.3 - v cntl v quiescent current i cntl i out =0a - 1 3 ma standby current i stby i out =0a, v refen =0v - 1 10 a output offset voltage (note1) v os i out =0a -20 - +20 mv load regulation (note2) t v load i out =1.5a - 0.5 2 % shutdown threshold v ih enable, refen rising 0.7 - - v v il shutdown, refen falling - - 0.2 v current limit i cl-source sourcing 2 - - a i cl-sink sinking 2 - - a soft-start period t ss v out =1.25v - 1.5 - ms thermal shutdown t sd - 160 - c thermal shutdown hysterisis t sdh - 30 - c note 1: v os offset is the voltage measurement defined as v out subtracted from v refen . note 2: regulation is measured at constant junction temper ature by using a 5ms current pulse. devices are tested for load regulation in the load range from 0a to 1.5a.
4/9 axelite confidential materials, do not copy or distribute without written consent. rev.1.5 aug.24, 2011 a x1250s ? application circuit c3 1 2 3 4 AX1250S refen vin vout vcntl gnd c1 470uf (low esr) c4 en c2 1uf r1 r2 100k 100k 47uf v in =2.5v/1.8v/1.5v v cntl =3.3v r tt 5~8 r tt =50 /33 /25 c3=10uf(ceramic) + 1000uf under t he worst case testing condition on off ? application information input capacitor and la yout consideration place the input bypass capacitor as clos e as possible to t he AX1250S. a low esr capacitor larger than 470uf is recommended for the input c apacitor. use short and wide traces to minimize parasitic resistance and inductan ce. inappropriate layout may result in large parasitic inductance and cause undesired oscillation between AX1250S and the preceding power converter. consideration while designs the resistance of voltage divider make sure the sinking current capability of pull-down nmos if the lower resistance was chosen so that the voltage on v refen is below 0.2v. in addi tion, the capacitor and voltage divider form the low pass filter. there are two reasons doing this design; one is for output voltage soft-start while a nother is for noise immunity.
5/9 axelite confidential materials, do not copy or distribute without written consent. rev.1.5 aug.24, 2011 a x1250s thermal considerations the AX1250S series can deliver a current of up to 1.5a over the full operating junction temperature range. however, the maximu m output current must be dated at higher ambient temperature to ensure the junction temperature does not exceed 125c. with all possible conditions, the junction temperature must be within the range specified under operating conditions. power dissipation can be calculated based on th e output current and the voltage drop across regulator. pd = (v in - v out ) i out + v in i q the final operating junction temperature for any set of conditions can be estimated by the following t hermal equation: pd (max) = (t j (max) - t a ) / ja where t j (max) is the maximum junction te mperature of the die (125 c ) and t a is the maximum ambient temperatur e. the junction to ambient thermal resistance ( ja ) for sop-8l p ackage at recommended minimum footprint is 60 c/w on 1.5 in 2 and multi-layer pcb layout . the maximum power dissipation at t a = 25c can be calculat ed by following formula: pd (max) = (125c - 25c) / 60c /w = 1.67w the thermal resistance ja of sop-8l is determined by the package design and the pcb design. however, the package design has been decided. if possible, it's useful to increase thermal performance by the pcb design. the thermal resistance can be decreased by adding wide copper to v cntl pins. we have to consider the copper couldn't stretch infinitely and av oid the tin overflow.
6/9 axelite confidential materials, do not copy or distribute without written consent. rev.1.5 aug.24, 2011 a x1250s ? typical characteristics transient test transient test v in =2.5v, v out =1.25v, v cntl =3.3v, i out =-1.5a~1.5a v in =1.8v, v out =0.9v, v cntl =3.3v, i out =-1.5a~1.5a transient test soft-start v in =1.5v, v out =0.75v, v cntl =3.3v, i out =-1.5a~1.5a v in =1.5v, v out =0.75v , v cntl =3.3v source current limit sink current limit v in =1.5v, v out =0.75v , v cntl =3.3v v in =1.5v, v out =0.75v , v cntl =3.3v
7/9 axelite confidential materials, do not copy or distribute without written consent. rev.1.5 aug.24, 2011 a x1250s ? typical characteristics (countinous) ddr-ii ddr-ii ddr-i ddr-i ddr-ii ddr-ii
8/9 axelite confidential materials, do not copy or distribute without written consent. rev.1.5 aug.24, 2011 a x1250s ? typical characteristics (countinous) ddr-iii ddr-iii ddr-i ddr-ii ddr-iii
9/9 axelite confidential materials, do not copy or distribute without written consent. rev.1.5 aug.24, 2011 a x1250s ? package outlines detail a l h e a a2 a1 e d 7 (4x) b y c detail a symbol dimensions in millimeters dimensions in inches min. nom. max. min. nom. max. a - - 1.75 - - 0.069 a 1 0.1 - 0.25 0.04 - 0.1 a 2 1.25 - - 0.049 - - c 0.1 0.2 0.25 0.0075 0.008 0.01 d 4.7 4.9 5.1 0.185 0.193 0.2 e 3.7 3.9 4.1 0.146 0.154 0.161 h 5.8 6 6.2 0.228 0.236 0.244 l 0.4 - 1.27 0.015 - 0.05 b 0.31 0.41 0.51 0.012 0.016 0.02 e 1.27 bsc 0.050 bsc y - - 0.1 - - 0.004 0 o - 8 o 0 o - 8 o mold flash shall not exceed 0.25mm per side jedec outline: ms-012 aa
|
